Application specific integrated circuits (ASICs) are widely used to implement sophisticated electronic circuits for mass production. An application specific integrated circuit is a semi-custom integrated circuit that uses a cell library of circuit or logical cells that are instantiated to form the overall function of the ASIC.
ASICs are developed in a number of different ways. One approach is to construct a prototype using discrete components wired together on a bread board or an etched printed circuit board. The prototype is tested and debugged to be sure the proper function of the ASIC. The prototype definition is then migrated into a monolithic integrated circuit, an ASIC design.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements connected together to perform a function. Cells are provided as part of an ASIC design technology library that defines which cells are implemented in a specific circuit design.
In a few years technology has moved very quickly from 180 nm to 65 nm or even below channel widths. The need to constantly build smaller and faster circuits means that designers and electronic companies need to move their existing designs to the latest technology as quickly and efficiently as possible to avoid losing the any opportunity to market their products and designs. Generally, transferring an old design to a new technology requires engineers to go through a long and tedious design process starting over with the RTL description of the design. A company that has several design teams participating at multiple stages of the design process will therefore have to expend a large amount of time and cost for their teams to go through the design process starting with the RTL description to produce a new netlist.
A netlist is a detailed interconnection listing logic gate cells, blocks, black-boxes or other elements in a particular technology from which mask layouts may be automatically produced for integrated circuit fabrication. The netlist may be in Verilog or VHDL format and is generated from synthesis tools, such as the RTL Compiler synthesis tool by Cadence Design Systems, Inc.
There are special processes involved prior to releasing a netlist to the back-end physical design flow. These time consuming and demanding steps include design-for-test (DFT) synthesis and scan-chain stitching, observation point insertion to improve DFT coverage, selection of good data path architecture to meet design timing requirements, and any engineering-change-order (ECO) level changes made to the netlists that are not reflected in the register transfer level (RTL) hardware description.
It may be desirable to migrate an existing ASIC design from one set of library cells to a new set of library cells without any substantial loss or substantial change to the function of the original integrated circuit design. This may be to obtain a second source of wafer fabrication (“silicon foundry”) for the ASIC design that has additional capacity. Another reason to migrate the ASIC design may be to improve performance and/or reduce die size and costs.
One problem designers face today in migrating one circuit design to a new technology is the time and effort generally required to manually update the library-cells associated with instances in a netlist. Such manual effort needed for developing and updating the cells is time consuming and prone to errors.
Another common problem faced today is related to yield improvements. Based on the results of a product testing, a company may find that a given set of library cells in their technology libraries give lower yields in post production. In such cases, the company would ideally desire to have the ability to efficiently make small changes to their current designs by removing the lower yielding cells or substituting the lower yielding cells with higher yielding ones without having to repeat the design flow for designing an entire ASIC design.
The typical approach to migrating an ASIC design from one technology library to another is to start from the register transfer level (RTL) hardware description input and repeat the entire ASIC design flow there-from, including performing a complete synthesis once again of the entire ASIC design. This approach of migrating an ASIC design is a long and strenuous process requiring multiple levels of design resources, including ASIC design engineers, that can be quite costly.
Although other migration approaches may begin from the netlist level may exist, they are often not employed because of certain limitations. For example, Solutions starting from netlist, for instance, have the basic limitation of being incapable of handling scan-stitched netlists. In effect, the scan-configuration is completely broken and requires full scan-resynthesis. Additionally, clock-gating integrated cells are often not handled appropriately. Consequently, the constraint migration to the new netlist becomes incomplete. These limitations, therefore, render these existing solutions practically useless.
It is desirable to overcome the foregoing deficiencies of prior netlist migration and provide fast turnaround times with minimal effort on part of the design engineers.